SH7205 Datasheet, PDF (395/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
Figure 11.1 is a block diagram of the DMAC.
DREQ0 to DREQ3
DACK0 to DACK3
TEND0 to TEND3
DACT0 to DACT3
BSC
DMA request
DMA acknowledge
DMA end
(DMATCk_N)
DMA active for source
(DMAACTSk_N)
DMA active
for destination
(DMAACTDk_N)
DMA interrupt request
DMA common
interrupt request
CPU
control signal
DMAC core
DMA request arbitration
DMAC
control
circuit
DMA
read
bus
DMA
write
bus
Data
buffer
CPU
interface
Register
interface
Current
register
Reload
register
Ch0 DMA setting data
:
Chn DMA setting data
Ch0 DMA transfer data
:
Chn DMA transfer data
Register
DMAC
(Working register)
Working register
control
Source address
register
Destination address
register
Byte count register
Mode register
[Legend]
DMA request arbitration: Arbitrates DMA requests and generates request signals to DMAC core.
CPU interface:
Register interface:
Read/write control of register access from CPU
Register access control from CPU and DMAC core
Register:
Working register:
Stores DMAC setting data and transfer data.
Register that DMAC core references (access from CPU prohibited)
DMA control circuit:
Data buffer:
DMAC control circuit
DMA data buffer
Figure 11.1 DMAC Block Diagram
Rev. 1.00 Mar. 25, 2008 Page 363 of 1868
REJ09B0372-0100