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SH7205 Datasheet, PDF (1759/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
Section 32 List of Registers
Module Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Name Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
RCAN-TL1 MBn_DATA_67_1
(n = 0 to 31)
MSG_DATA_6
MSG_DATA_7
MBn_CONTROL 

NMC


1_1 (n = 0)




MBC[2:0]
DLC[3:0]
MBn_CONTROL 

NMC
ATX
DART
1_1 (n = 1 to 31)




MBC[2:0]
DLC[3:0]
MBn_TIMESTAM TS15
TS14
TS13
TS12
TS11
TS10
TS9
TS8
P_1 (n = 0 to 15,
TS7
TS6
TS5
TS4
TS3
TS2
TS1
TS0
30, 31)
MBn_TTT_1
(n = 24 to 30)
TTT15
TTT7
TTT14
TTT6
TTT13
TTT5
TTT12
TTT4
TTT11
TTT3
TTT10
TTT2
TTT9
TTT1
TTT8
TTT0
MBn_TTCONTR
TTW[1:0]
Offset[5:0]
OL_1





(n = 24 to 29)
rep_factor[2:0]
ADC
ADDRA






ADDRB






ADDRC






ADDRD






ADDRE






ADDRF






ADDRG






ADDRH






ADCSR
ADF
ADIE
ADST

TRGS[3:0]
CKS[1:0]
MDS[2:0]
CH[2:0]
Rev. 1.00 Mar. 25, 2008 Page 1727 of 1868
REJ09B0372-0100