SH7205 Datasheet, PDF (1247/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
Bit
11
10, 9
8
Bit Name
Initial
Value
R/W Description
SUREQCLR 0
R*¹/W*² SUREQ Bit Clear
When the host controller function is selected,
setting this bit to 1 clears the SUREQ bit to 0.
Set this bit to 1 when communication has stopped
with SUREQ being 1 during the setup transaction.
However, in normal setup transactions, the SUREQ
bit is automatically cleared to 0 upon completion of
the transaction; therefore, processing for clearing
the SUREQ bit is not necessary.
0: No effect
1: Clears the SUREQ bit to 0.
Note: Controlling the SUREQ bit through this bit
must be done while UACT is 0 and thus
communication is halted or while no transfer
is being performed with bus disconnection
detected.

Undefined R
Reserved
Undefined values are read from these bits. The
write value should always be 0.
SQCLR
0
R*¹/W*² Toggle Bit Clear*³
Specifies DATA0 as the expected value of the
sequence toggle bit for the next transaction during
the DCP transfer.
0: No effect
1: Specifies DATA0.
Note: Do not set the SQCLR and SQSET bits to 1
simultaneously.
Rev. 1.00 Mar. 25, 2008 Page 1215 of 1868
REJ09B0372-0100