SH7205 Datasheet, PDF (1113/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 AND/NAND Flash Memory Controller (FLCTL)
23.3.4 Address Register (FLADR)
FLADR is a 32-bit readable/writable register that specifies the value to be output as an address.
The address of the size specified by ADRCNT[1:0] in the command control register is output
sequentially from ADR1 in byte units. By the sector access address specification bit (ADRMD) of
the command control register, it is possible to specify whether the sector number set in the address
data bits is converted into an address to be output to the flash memory.
• When ADRMD = 1
Bit: 31
Initial value: 0
R/W: R/W
30
0
R/W
29
0
R/W
28 27
ADR4[7:0]
0
0
R/W R/W
26
0
R/W
25
0
R/W
24
0
R/W
23
0
R/W
22
0
R/W
21
0
R/W
20 19
ADR3[7:0]
0
0
R/W R/W
18
0
R/W
17
0
R/W
16
0
R/W
Bit: 15
Initial value: 0
R/W: R/W
14
0
R/W
13
0
R/W
12 11
ADR2[7:0]
0
0
R/W R/W
10
0
R/W
9
0
R/W
8
0
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
3
ADR1[7:0]
0
0
R/W R/W
2
0
R/W
1
0
R/W
0
0
R/W
Initial
Bit
Bit Name Value R/W
31 to 24 ADR4[7:0] H'00 R/W
23 to 16 ADR3[7:0] H'00 R/W
15 to 8 ADR2[7:0] H'00 R/W
7 to 0 ADR1[7:0] H'00 R/W
Description
Fourth Address Data
Specify 4th data to be output to flash memory as an
address when ADRMD = 1.
Third Address Data
Specify 3rd data to be output to flash memory as an
address when ADRMD = 1.
Second Address Data
Specify 2nd data to be output to flash memory as an
address when ADRMD = 1.
First Address Data
Specify 1st data to be output to flash memory as an
address when ADRMD = 1.
Rev. 1.00 Mar. 25, 2008 Page 1081 of 1868
REJ09B0372-0100