SH7205 Datasheet, PDF (230/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 7 Interrupt Controller (INTC)
7.4.6 On-Chip Peripheral Module Interrupts
On-chip peripheral module interrupts are generated by the following on-chip peripheral modules:
• Direct memory access controller (DMAC)
• USB2.0 host/function module (USB)
• Compare match timer (CMT)
• Watchdog timer (WDT)
• Multi-function timer pulse unit 2 (MTU2)
• I²C bus interface 3 (IIC3)
• Serial communications interface with FIFO (SCIF)
• Serial sound interface with FIFO (SSIF)
• Synchronous serial communications unit (SSU)
• A/D converter (ADC)
• 2D engine (2DG)
• AT attachment packet interface (ATAPI)
• AND/NAND flash memory controller (FLCTL)
• Realtime clock (RTC)
• Controller area network (RCAN-TL1)
As every source is assigned a different interrupt vector, the source does not need to be identified in
the exception service routine. A priority level in a range from 0 to 15 can be set for each module
by interrupt priority registers 06 to 21 (C0IPR06 to C0IPR21 and C1IPR06 to C1IPR21). The on-
chip peripheral module interrupt exception handling sets the I3 to I0 bits in the SR to the priority
level of the accepted on-chip peripheral module interrupt.
7.4.7 Inter-Processor Interrupts
Inter-processor interrupts are generated by setting the inter-processor interrupt control registers
(C0IPCR15 to C0IPCR08 and C1IPCR15 to C1IPCR08). Interrupts can be generated from CPU0
to CPU1 and vise versa.
When the inter-processor interrupt enable registers (C0IPER and C1IPER) are set, interrupt
requests from the inter-processor interrupt control registers are enabled and sent to the CPU.
Rev. 1.00 Mar. 25, 2008 Page 198 of 1868
REJ09B0372-0100