SH7205 Datasheet, PDF (1110/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 AND/NAND Flash Memory Controller (FLCTL)
Initial
Bit
Bit Name Value R/W Description
26
ADRMD 0
R/W Sector Access Address Specification
This bit is invalid in command access mode. This bit is
valid only in sector access mode. (Set this bit to 1 when
using AND-type flash memory.)
0: The value of the address register is handled as a
sector address. Use this value usually in sector
access.
1: The value of the address register is output as the
address of flash memory.
Note: Clear this bit to 0 in continuous sector access.
25
CDSRC 0
R/W Data Buffer Specification
Specifies the data buffer to be read from or written to in
the data stage in command access mode.
0: Specifies FLDATAR as the data buffer.
1: Specifies FLDTFIFO as the data buffer.
24
DOSR
0
R/W Status Read Check
Specifies whether or not the status read is performed
after the second command has been issued in
command access mode.
0: Performs no status read
1: Performs status read
23, 22 —
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
21
SELRW 0
R/W Data Read/Write Specification
Specifies the direction of read or write in data stage.
0: Read
1: Write
20
DOADR 0
R/W Address Stage Execution Specification
Specifies whether or not the address stage is executed
in command access mode.
0: Performs no address stage
1: Performs address stage
Rev. 1.00 Mar. 25, 2008 Page 1078 of 1868
REJ09B0372-0100