SH7205 Datasheet, PDF(1334/1904 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

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SH7205 Datasheet, PDF (1334/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

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Section 25 AT Attachment Packet Interface (ATAPI)

Table 25.3 ATAPI Packet Command Task File Register Map

(These resisters are allocated to the ATAPI or ATA device, but not to this module.)

Address

Read Register

Pin Address

(IDECS[1:0]#,

Write Register IDEA[2:0])

Access Size*1

(Available Bit Register

Size)

Location

H'FFFECC00 Data

Data

HL-LLL

32 (16)*2

Drive

H'FFFECC04 Error

Function

HL-LLH

32 (8)*3

Drive

H'FFFECC08 Interrupt source ï£§

HL-LHL

32 (8)*3

Drive

H'FFFECC0C ï£§

ï£§

HL-LHH

32 (8)*3

Drive

H'FFFECC10 Byte count low Byte count low HL-HLL

32 (8)*3

Drive

H'FFFECC14 Byte count high Byte count high HL-HLH

32 (8)*3

Drive

H'FFFECC18 Device select

Device select HL-HHL

32 (8)*3

Drive

H'FFFECC1C Status

Command

HL-HHH

32 (8)*3

Drive

H'FFFECC38 Alternate status Device control LH-HHL

32 (8)*3

Drive

Notes: 1. The CPU must access these registers in longword (32-bit) units. Byte and word

accesses are prohibited.

2. Bits 15 to 0 of the data bus are used.

3. Bits 7 to 0 of the data bus are used.

Rev. 1.00 Mar. 25, 2008 Page 1302 of 1868

REJ09B0372-0100

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