SH7205 Datasheet, PDF (1120/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 AND/NAND Flash Memory Controller (FLCTL)
Initial
Bit
Bit Name Value
18
AC0CLR 0
17
DREQ1EN 0
16
DREQ0EN 0
15 to 10 —
All 0
9
ECERB 0
R/W Description
R/W FLDTFIFO Clear
Clears FLDTFIFO.
0: Retains the FLDTFIFO value. In flash-memory
access, this bit should be cleared to 0.
1: Clears FLDTFIFO. After FLDTFIFO has been
cleared, this bit should be cleared to 0.
R/W FLECFIFODMA Request Enable
Enables or disables the DMA transfer request issued
from FLECFIFO.
0: Disables the DMA transfer request issued from
FLECFIFO
1: Enables the DMA transfer request issued from
FLECFIFO
R/W FLDTFIFODMA Request Enable
Enables or disables the DMA transfer request issued
from FLDTFIFO.
0: Disables the DMA transfer request issued from the
FLDTFIFO
1: Enables the DMA transfer request issued from the
FLDTFIFO
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/(W)* ECC Error
Indicates the result of ECC error detection. This bit is
set to 1 if an ECC error occurs while flash memory is
read in sector access mode.
No interrupt occurs even if this bit is set to 1.
This bit is a flag. 1 cannot be written to this bit. Only 0
can be written to clear the flag.
0: Indicates that no ECC error occurs (Latched ECC is
all 0.)
1: Indicates that an ECC error occurs
Rev. 1.00 Mar. 25, 2008 Page 1088 of 1868
REJ09B0372-0100