SH7205 Datasheet, PDF (447/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
11.3.20 DMA Two-Dimensional Addressing Next Block Offset Register (DM2DNBOSTm)
DM2DMBOSTm is a register used to set the offset for calculating the start address of the next
block in two-dimensional addressing.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DNBOST[31:16]
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15
Initial value: -
R/W: R/W
14
-
R/W
13
-
R/W
12
-
R/W
11
-
R/W
10
-
R/W
9
8
7
6
DNBOST[15:0]
-
-
-
-
R/W R/W R/W R/W
5
-
R/W
4
-
R/W
3
-
R/W
2
-
R/W
1
-
R/W
0
-
R/W
Initial
Bit
Bit Name Value
R/W Description
31 to 0
DNBOST Undefined R/W DMA2D Next Block Offset Byte Count
[31:0]
These bits are used to set the number of bytes to be added
to the current source or destination address to calculate the
start address of the next block when DMA transfer of one
block ends in two-dimensional addressing. Set a two’s
complement number in these bits.
Rev. 1.00 Mar. 25, 2008 Page 415 of 1868
REJ09B0372-0100