SH7205 Datasheet, PDF (954/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 19 Serial Sound Interface with FIFO (SSIF)
19.4.5 Receive Operation
Like transmission, reception can be controlled either by DMA or interrupt.
Figures 19.22 and 19.23 show the flow of operation.
When disabling the SSIF module, the clock* must be kept supplied to the SSIF until the IIRQ bit
indicates that the module is in the idle state.
Note: * Input clock from the SSISCK pin when SCKD = 0.
Oversampling clock when SCKD = 1.
Rev. 1.00 Mar. 25, 2008 Page 922 of 1868
REJ09B0372-0100