SH7205 Datasheet, PDF (279/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 9 Cache
Initial
Bit
Bit Name Value R/W
11
ICF
0
R/W
10, 9 
All 0 R
8
ICE
0
R/W
7 to 4 
All 0 R
3
OCF
0
R/W
2

1
WT
0
R
0
R/W
0
OCE
0
R/W
Description
Instruction Cache Flush
Writing 1 flushes all instruction cache entries (clears the V
and LRU bits of all instruction cache entries to 0). Always
reads 0. Write-back to external memory is not performed
when the instruction cache is flushed.
Reserved
These bits are always read as 0. The write value should
always be 0.
Instruction Cache Enable
Indicates whether the instruction cache function is enabled
or disabled.
0: Instruction cache disabled.
1: Instruction cache enabled.
Reserved
These bits are always read as 0. The write value should
always be 0.
Operand Cache Flush
Writing 1 flushes all operand cache entries (clears the V,
U, and LRU bits of all operand cache entries to 0). Always
reads 0. Write-back to external memory is not performed
when the operand cache is flushed.
Reserved
This bit is always read as 0. The write value should always
be 0.
Write Through
Selects write-back mode or write-through mode.
0: Write-back mode
1: Write-through mode
Operand Cache Enable
Indicates whether the operand cache function is enabled
or disabled.
0: Cache disabled.
1: Cache enabled.
Rev. 1.00 Mar. 25, 2008 Page 247 of 1868
REJ09B0372-0100