SH7205 Datasheet, PDF (222/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 7 Interrupt Controller (INTC)
7.3.15 DMA Transfer Request Enable Registers 0 to 8 (DREQER0 to DREQER8)
DREQER0 to DREQER8 are 8-bit readable/writable registers that enable or disable DMA transfer
requests from on-chip peripheral modules, and enable or disable CPU interrupts.
Bit: 7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
(1) DREQER0
Bit Bit Name
7 to 4 
Initial
Value R/W
All 0 R
3
CMT CMI3 0
R/W
2
CMT CMI2 0
R/W
1
CMT CMI1 0
R/W
0
CMT CMI0 0
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
DMA Transfer Enable
These bits enable or disable DMA transfer requests and
CPU interrupt requests.
0: DMA transfer request is disabled and CPU interrupt
request is enabled
1: DMA transfer request is enabled and CPU interrupt
request is disabled
(2) DREQER1
Bit Bit Name
7 to 5 
Initial
Value R/W
All 0 R
4
MTU TGI4A 0
R/W
3
MTU TGI3A 0
R/W
2
MTU TGI2A 0
R/W
1
MTU TGI1A 0
R/W
0
MTU TGI0A 0
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
DMA Transfer Enable
These bits enable or disable DMA transfer requests and
CPU interrupt requests.
0: DMA transfer request is disabled and CPU interrupt
request is enabled.
1: DMA transfer request is enabled and CPU interrupt
request is disabled.
Rev. 1.00 Mar. 25, 2008 Page 190 of 1868
REJ09B0372-0100