SH7205 Datasheet, PDF (1168/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
24.3.2 System Configuration Control Register 1 (SYSCFG1)
SYSCFG1 is a register that enables high-speed operation on PORT1, controls the DP and DM pins
and access cycles for access to this module.
This register is initialized by a power-on reset.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
— HSE — DRPD —
BWAIT[3:0]
Initial value: -
-
-
-
-
-
-
-
0
-
0
-
1
1
1
1
R/W: R
R
R
R
R
R
R
R R/W R R/W R R/W R/W R/W R/W
Bit
Bit Name
15 to 8 
7
HSE
6

Initial
Value
R/W
Undefined R
0
R/W
Undefined R
Description
Reserved
Undefined values are read from these bits. The write
value should always be 0.
PORT1 High-Speed Operation Enable
Enables or disables high-speed operation on PORT1.
When HSE = 0, the PORT1 performs low-speed or
full-speed operation.
Set HSE to 0 when connection of a low-speed function
device to PORT1 has been detected.
When HSE = 1, this module executes the reset
handshake protocol, and automatically drives the
PORT1 to perform high-speed or full-speed operation
according to the protocol execution result.
0: High-speed operation is disabled (full-speed or low-
speed)
1: High-speed operation is enabled (this module
detects the communication rate)
Note: This bit should be modified after detecting
device connection (after detecting the ATTCH
interrupt) and before executing a USB bus reset
(before setting USBRESET to 1).
Reserved
Undefined value is read from this bit. The write value
should always be 0.
Rev. 1.00 Mar. 25, 2008 Page 1136 of 1868
REJ09B0372-0100