SH7205 Datasheet, PDF (1153/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 AND/NAND Flash Memory Controller (FLCTL)
23.7 Usage Notes
23.7.1 Writing to the Control-Code Area when 4-Symbol ECC Circuit is in Use
Follow the procedure given below to write to the control-code area when the 4-symbol ECC
circuit is in use. If this procedure is not followed, correctly writing to the control-code area of the
flash memory will not be possible.
Start of writing to a sector or consecutive sectors
Start
If the 3-symbol ECC circuit has been enabled,
the below flow for writting is not necessary.
Store the data to be written to the control-code
area in high-speed internal RAM(RAM1).
Settings for DMA transfer
Source:High-speed RAM(RAM1)
Destination:FLECFIFO
Number of data for single-operand transfer:4 DMA
transfer mode:Pipeline transfer
Set the FLINTDMACR.FIFOTRG[0] bit (to 1).
No
DMA
Is the 4ECCEN
bit in FLCMNCR 1?
Yes
Has the CPU or
DMAC been selected
in FLINTDMACR to
handle transfer from
FLECFIFO?
CPU
Normal settings for writing
Set FLTRCR to H'01.
Start the transfer.
Is the number of empty
longwords indicated by
No
FLDTCNTR.ECFLW eight?
Yes
Store the data to be written to the
control code area in FLECFIFO.
Store the data to be written to
the data area in FLDTFIFO.
To the flow for normal
programming
FLCMDCR
No
SCTCNT==0?
Yes
End
Figure 23.19 Writing Procedure to the Control-Code Area when 4-Symbol ECC is Used
Rev. 1.00 Mar. 25, 2008 Page 1121 of 1868
REJ09B0372-0100