SH7205 Datasheet, PDF (1324/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
24.4.8 Isochronous Transfers (PIPE1 and PIPE2)
This module has the following functions pertaining to isochronous transfers.
• Notification of isochronous transfer error information
• Interval counter (specified by the IITV bit)
• Isochronous IN transfer data setup control (IDLY function)
• Isochronous IN transfer buffer flush function (specified by the IFIS bit)
This module does not support the High Bandwidth transfers of isochronous transfers.
When operation as a host controller is selected and two pipes are used for isochronous transfer at
the same time, observe the restrictions on packets stated in the USB 2.0 Specification, section
5.6.3, Isochronous Transfer Packet Size Constraints.
(1) Interval Counter
(a) Outline of Operation
The isochronous interval can be set using the IITV bits in PIPEPERI. The interval counter enables
the functions shown in table 24.27 when the function controller function is selected. When the
host controller function is selected, this module generates the token issuance timing. When the
host controller function is selected, the interval counter operation is the same as the interrupt
transfer operation.
Table 24.27 Functions of the Interval Counter when the Function Controller Function is
Selected
Transfer
Direction
IN
OUT
Function
IN buffer flush function
Notifies that a token not
being received
Conditions for Detection
When a token cannot be normally received in the
interval frame during an isochronous IN transfer
When a token cannot be normally received in the
interval frame during an isochronous OUT transfer
The interval count is carried out when an SOF is received or for interpolated SOFs, so the
isochronism can be maintained even if an SOF is damaged. The frame interval that can be set is
the 2^IITV frame or 2 µ ^IITV frames.
Rev. 1.00 Mar. 25, 2008 Page 1292 of 1868
REJ09B0372-0100