SH7205 Datasheet, PDF(1409/1904 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

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SH7205 Datasheet, PDF (1409/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

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Section 26 2D Graphics Engine (2DG)

Table 26.5 FBFA Bit Details

FBFA

(Register Value) Fb

00 (Initial value) Î±b

01

1

10

Î±b

11

0

Fa

(1-Î±b)Î±a

0

(1-Î±b)

1

Remarks

2-input plane processing is performed.

Î±out = Fb+Fa

1-input plane processing is performed.

Î±out = Î±b

Blending without using Î±a is performed.

Î±out = Î±b

Only the SA or GR_BRDCOL register value is output.

Î±out = Î±a

â¢ When the fill operation has been selected (BTYPE bits in BR_BLTMODE = 10), the GCOLR

bit should be set to 1 and the FBFA bits are arbitrary (basically cleared to 00 because fill

operation with blending is performed.)

â¢ The AFTER_A bits are valid only when GALFA = 1.

â¢ FBFA should be set to 01 when chromakey processing has been selected.

â¢ GCOLR should be set to 1 to perform fill operation (BTYPE in GR_BLTMODE = 10).

Rev. 1.00 Mar. 25, 2008 Page 1377 of 1868

REJ09B0372-0100

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