SH7205 Datasheet, PDF (927/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 19 Serial Sound Interface with FIFO (SSIF)
19.3.2 Status Register (SSISR)
SSISR consists of status flags indicating the operational status of the SSIF module and bits
indicating the current channel numbers and word numbers.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20
-
-
-
-
UIRQ OIRQ IIRQ
-
-
-
-
-
Initial value: -
-
-
-
0
0
1
-
-
-
-
-
R/W: R
R
R
R R/(W)* R/(W)* R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
R/W: R
R
R
R
R
R
R
R
R
R
R
R
Note: * The bit can be read or written to. Writing 0 initializes the bit, but writing 1 is ignored.
19 18 17 16
-
-
-
-
-
-
-
-
R
R
R
R
3
2
CHNO[1:0]
0
0
R
R
1
0
SWNO IDST
1
1
RR
Bit
31 to 28
27
Bit Name
—
UIRQ
Initial
Value
R/W Description
Undefined R
Reserved
The read value is undefined. The write value should
always be 0.
0
R/(W)* Underflow Error Interrupt Status Flag
This status flag indicates that data was supplied at a
lower rate than was required.
In either case, this bit is set to 1 regardless of the value
of the UIEN bit and can be cleared by writing 0 to this
bit.
If UIRQ = 1 and UIEN = 1, an interrupt occurs.
• TRMD = 0 (Receive mode)
If UIRQ = 1, SSIRDR was read while the FIFO is
empty (DC = H’0).
This can cause invalid receive data to be stored,
which may lead to corruption of multi-channel data.
• TRMD = 1 (Transmit mode)
If UIRQ = 1, SSITDR did not have data written to it
before it was required for transmission. This will
lead to the same sample being transmitted once
more and a potential corruption of multi-channel
data. This error is more serious than an underflow in
receive mode since the SSIF will output erroneous
data.
Note: When an underflow error occurs, the current data
in the data buffer of this module is transmitted
until the next data is written.
Rev. 1.00 Mar. 25, 2008 Page 895 of 1868
REJ09B0372-0100