SH7205 Datasheet, PDF (963/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 20 Controller Area Network (RCAN-TL1)
• Timer
The Timer function is the functional entity, which provides RCAN-TL1 with support for
transmitting messages at a specific time frame and recording the result.
The Timer is a 16-bit free running up counter which can be controlled by the CPU. It provides
one 16-bit Compare Match Register to compare with Local Time and two 16-bit ones to
compare with Cycle Time. The Compare Match Registers can generate interrupt signals and
clear the Counter.
The clock period of this Timer offers a wide selection derived from the system clock or can be
programmed to be incremented with one nominal bit timing of CAN Bus.
Contains registers such as TCNTR, TTCR0, CMAX_TEW, RETROFF, TSR, CCR, CYCTR,
RFMK, TCMR0, TCMR1, TCMR2 and TTTSEL.
• CAN Interface
This block conforms to the requirements for a CAN Bus Data Link Controller which is
specified in Ref. [2, 4]. It fulfils all the functions of a standard DLC as specified by the OSI 7
Layer Reference model. This functional entity also provides the registers and the logic which
are specific to a given CAN bus, which includes the Receive Error Counter, Transmit Error
Counter, the Bit Configuration Registers and various useful Test Modes. This block also
contains functional entities to hold the data received and the data to be transmitted for the
CAN Data Link Controller.
Rev. 1.00 Mar. 25, 2008 Page 931 of 1868
REJ09B0372-0100