SH7205 Datasheet, PDF(1038/1904 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

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SH7205 Datasheet, PDF (1038/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

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Section 20 Controller Area Network (RCAN-TL1)

Figure 20.15 shows allowed state transitions.

ï£§ Please don't set MCR5 (Sleep Mode) without entering Halt Mode.

ï£§ After MCR1 is set, please don't clear it before GSR4 is set and RCAN-TL1 enters Halt

Mode.

Power On/SW Reset

clear MCR1

and MCR5

set MCR1*3

Reset

clear MCR0

and GSR3 = 0

Transmission

Reception

clear MCR5*1

Halt Request

clear MCR5

set MCR1*4

except Transmitter/Receiver/BusOff, if MCR6 = 0

BusOff or except Transmitter/Receiver, if MCR6 = 1

Halt Mode

set MCR5

clear MCR1*2

Sleep Mode

Figure 20.15 Halt Mode/Sleep Mode

Notes: 1. MCR5 can be cleared by automatically by detecting a dominant bit on the CAN Bus if

MCR7 is set or by writing â0â.

2. MCR1 is cleared in SW. Clearing MCR1 and setting MCR5 have to be carried out by

the same instruction.

3. MCR1 must not be cleared in SW, before GSR4 is set. MCR1 can be set automatically

in HW when RCAN-TL1 moves to Bus Off and MCR14 and MCR6 are both set.

4. When MCR5 is cleared and MCR1 is set at the same time, RCAN-TL1 moves to Halt

Request. Right after that, it moves to Halt Mode with no reception/transmission.

The following table shows conditions to access registers.

Rev. 1.00 Mar. 25, 2008 Page 1006 of 1868

REJ09B0372-0100

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