SH7205 Datasheet, PDF (660/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.7.8 Contention between Buffer Register Write and TCNT Clear
When the buffer transfer timing is set at the TCNT clear by the buffer transfer mode register
(TBTM), if TCNT clear occurs in the T2 state of a TGR write cycle, the data that is transferred to
TGR by the buffer operation is the data before write.
Figure 12.103 shows the timing in this case.
Pφ
Address
Write signal
TCNT clear
signal
Buffer transfer
signal
Buffer register
TGR write cycle
T1
T2
Buffer register
address
Buffer register write data
N
M
TGR
N
Figure 12.103 Contention between Buffer Register Write and TCNT Clear
Rev. 1.00 Mar. 25, 2008 Page 628 of 1868
REJ09B0372-0100