SH7205 Datasheet, PDF (347/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
(c) 8-Bit Bus Channel
If an 8-bit bus is selected by the external bus width select bits in the CSn control register, A25 to
A0 are enabled as address signals for byte units. Table 10.8 lists the data alignment corresponding
to byte addresses for different data sizes.
If byte strobe mode (WRMOD = 0) is selected, the WE0 signal is asserted only for write access; it
is not asserted for read access.
If one-write strobe mode (WRMOD = 1) is selected, the BC0 signal is asserted for both read and
write accesses. For write access, the write strobe signal WE is also asserted.
Table 10.8 Data Alignment (8-Bit Bus Channel)
Data Size
Byte Address
DATA
(Lower 2 Bits) [31:24] [23:16] [15:8] [7:0] [3]
WE/BC
[2] [1] [0]
Byte
0
×
×
×
O
*
*
*
L
1
×
×
×
O
*
*
*
L
2
×
×
×
O
*
*
*
L
3
×
×
×
O
*
*
*
L
Word
0 (1st)
×
×
×
O
*
*
*
L
1 (2nd)
×
×
×
O
*
*
*
L
2 (1st)
×
×
×
O
*
*
*
L
3 (2nd)
×
×
×
O
*
*
*
L
Longword
0 (1st)
×
×
×
O
*
*
*
L
1 (2nd)
×
×
×
O
*
*
*
L
2 (3rd)
×
×
×
O
*
*
*
L
3 (4th)
×
×
×
O
*
*
*
L
Note: The valid bits on the data bus for each data size are indicated by circles (O).
Crosses (×) indicate bus data bits that are undefined.
Asterisks (*) indicate write/byte control bits that are disabled (fixed at high level).
Rev. 1.00 Mar. 25, 2008 Page 315 of 1868
REJ09B0372-0100