SH7205 Datasheet, PDF (379/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
(14) Address Register Setting Values
(a) Supported SDRAM Configurations
Tables 10.16 to 10.21 list the SDRAM configurations supported for bus widths of 8, 16, and 32
bits. These tables are intended to help understand the relationships between the supported
SDRAM configurations and address multiplexing.
addr[25:0] is the logical address used by the CPU and DMAC in access to the SDRAM. The table
below lists how the settings of DSZ and DDBW determine which signals are output on the
SDRAM-access pins.
Rev. 1.00 Mar. 25, 2008 Page 347 of 1868
REJ09B0372-0100