SH7205 Datasheet, PDF (618/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(n) Output Waveform Control at Synchronous Counter Clearing in Complementary PWM
Mode
Setting the WRE bit in TWCR to 1 suppresses initial output when synchronous counter clearing
occurs in the Tb interval at the trough in complementary PWM mode and controls abrupt change
in duty cycle at synchronous counter clearing.
Initial output suppression is applicable only when synchronous clearing occurs in the Tb interval
at the trough as indicated by (10) or (11) in figure 12.56. When synchronous clearing occurs
outside that interval, the initial value specified by the OLS bits in TOCR is output. Even in the Tb
interval at the trough, if synchronous clearing occurs in the initial value output period (indicated
by (1) in figure 12.56) immediately after the counters start operation, initial value output is not
suppressed.
Counter start
Tb interval
TGRA_3
TCDR
Tb interval
Tb interval
TCNT_3
TGRB_3
TCNT_4
TDDR
H'0000
Positive phase
Negative phase
Output waveform is active-low
(1)
(2)
(3) (4) (5) (6) (7) (8)
(9)
(10) (11)
Figure 12.56 Timing for Synchronous Counter Clearing
Rev. 1.00 Mar. 25, 2008 Page 586 of 1868
REJ09B0372-0100