SH7205 Datasheet, PDF (141/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 4 Multi-Core Processor
4.3 Operation
4.3.1 Initializing This LSI
Use the following procedure to initialize this LSI. A sample program for the procedure is given in
figure 4.1.
1. After exit from the power-on reset state, the two CPUs execute power-on reset exception
handling. The CPUs should execute the same exception-handling routine.
2. In the power-on reset exception handling routine, each CPU should identify itself as CPU0 or
CPU1 by reading out CPUIDR and testing the value of the ID bit. The value read from the ID
bit is 0 for CPU0 and 1 for CPU1.
3. Each CPU then branches to the corresponding processing routine.
; In the power-on reset exception handling routine,
; read ID bit in CPUIDR and check the value.
MOVI20 #H'FFFC1404, R0
MOV.L @R0, R1
MOV.L #H'40000000, R2
AND
R2, R1
CMP/EQ R2, R1
BF
CPU0_ROUTINE
BRA
CPU1_ROUTINE
NOP
; Processing routine for CPU0
CPU0_ROUTINE:
:
:
; Processing routine for CPU1
CPU1_ROUTINE:
:
:
Figure 4.1 Example of a Program for Initialization of This LSI
Rev. 1.00 Mar. 25, 2008 Page 109 of 1868
REJ09B0372-0100