SH7205 Datasheet, PDF (1494/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 2D Graphics Engine (2DG)
(5) Blending in Output Block
The following describes the blending in the output block. The blending processor in the output
block supplies the output according to the following formula.
Cp = (Fc × Cdc) + (Fd × Cv)
Here, Fc and Fd are set using the FCFD bits of the MGR_MIXMODE register. Table 26.11 shows
the FCFD bit settings and the corresponding Fc and Fd values.
Table 26.11 Details of FCFD Bits of MGR_MIXMODE Register
FCFD (Bit Values) Fc
000 (Initial value)
1
001
αdc
010
1
011
0
100
0
Other than the above 
Fd
1 − αdc
1 − αdc
0
1
0

Remarks
When SE input image is premultiplied.
When SE input image is non-premultiplied.
Only graphics are output.
Only moving pictures are output.
Nothing is output. (Black screen)
Reserved
Moving pictures (color value = Cv)
SE input (color value = Cdc, α value = αdc)
Fd
Fc
Blending
by the output block
Constant-rate output from the output block (color value = Cp)
Figure 26.55 Summary of Output Block Operations during Blending
Rev. 1.00 Mar. 25, 2008 Page 1462 of 1868
REJ09B0372-0100