SH7205 Datasheet, PDF (1451/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 2D Graphics Engine (2DG)
• Blit function with blending (1)
This section shows an example of blending graphic images. Set the registers as follows:
• Set the GR_SABSET register to specify the number of pixels to be transferred to the SA/SB
buffers.
• Set the GR_DCSET register to specify the number of pixels to be transferred to the DC buffer.
• Set the BTYPE bits of the GR_BLTMODE register to 00 in order to specify blit operation for
blitter operating mode.
• To enable the blit function, set the SB_SETEN and SA_SETEN bits of the GR_BLTPLY
register to 1.
With the above settings, the blit function operates as follows:
1. By the GR_BLTPLY register settings, image data equal to the pixel count set in the
GR_SABSET register is transferred to the SA/SB buffers.
2. The pixel data transferred to the SA/SB buffers undergoes various processings set by the
relevant registers.
3. Image data equal to the number of pixels set in the GR_DCSET register is output to the DC
buffer.
The DMAC first transfers, memory-to-memory, pixels equal to the pixel count set in the register
from an SDRAM area specified by the CPU to the SA/SB buffers. After that, the DMAC transfers,
memory-to-memory, the pixel data processed in the 2DG from the DC buffer to the SDRAM area
specified by the CPU. As a result, the image on any area on the SDRAM can be replaced with
pixel data having undergone various image processings by the 2DG. In this case, the 2DG
performs input to the SA/SB buffers and output from the DC buffer.
Rev. 1.00 Mar. 25, 2008 Page 1419 of 1868
REJ09B0372-0100