SH7205 Datasheet, PDF (1859/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 33 Electrical Characteristics
IODREQ
(Device)
t_LI
t_LI
t_MLI
IODACK#
(Host)
(STOP)
IDEIOWR#
(Host)
(DDMARDY#)
IDEIORDY
(Device)
(HSTROBE)
IDEIORD#
(Host)
Read
IDED[15:0]
(Host)
t_SS
t_LI
t_ACK
t_IORDYZ
t_ACK
t_CVS
t_CVH
CRC
t_ACK
IDECS#[1:0]
IDEA[2:0]
Figure 33.73 Host Terminating Ultra DMA Data-Out Burst
Rev. 1.00 Mar. 25, 2008 Page 1827 of 1868
REJ09B0372-0100