SH7205 Datasheet, PDF (1099/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 AND/NAND Flash Memory Controller (FLCTL)
Section 23 AND/NAND Flash Memory Controller
(FLCTL)
The AND/NAND flash memory controller (FLCTL) provides interfaces for an external AND-type
flash memory and NAND-type flash memory. To take measures for errors specific to flash
memory, the FLCTL supports the ECC generation and error detection functions.
Up to 4-symbol ECC generator, error detector, and hardware error pattern generator have been
provided in addition to the 3-symbol ECC detector of the earlier products.
23.1 Features
(1) AND/NAND-Type Flash Memory Interface
• Interface directly connectable to AND/NAND-type flash memory
• Read or write in sector units (512 + 16 bytes) and ECC processing executed
• Read or write in byte units
• Supports large-block (2048 + 64 bytes) flash memory
• Supports addresses for 2 Gbits and more by extension to 5-byte addresses
Note: The FLCTL handles 512 + 16 bytes as a sector. For products with 2048 + 64 byte-pages,
the FLCTL divide a page into 512 +16 bytes units (i.e. four sectors per page) for
processing.
(2) Access Modes: The FLCTL can select one of the following two access modes.
• Command access mode: Performs an access by specifying a command to be issued from the
FLCTL to flash memory, address, and data size to be input or output. Read, write, or erasure of
data without ECC processing can be achieved.
• Sector access mode: Performs a read or write in sector units by specifying a sector address and
controls ECC generation and check. By specifying the number of sectors, the continuous
physical sectors can be read or written.
Rev. 1.00 Mar. 25, 2008 Page 1067 of 1868
REJ09B0372-0100