SH7205 Datasheet, PDF (708/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 13 Compare Match Timer (CMT)
13.2.3 Compare Match Counter (CMCNT)
CMCNT is a 16-bit register used as an up-counter. When the counter input clock is selected with
bits CKS[1:0] in CMCSR, and the STR bit in CMSTR is set to 1, CMCNT starts counting using
the selected clock. When the value in CMCNT and the value in compare match constant register
(CMCOR) match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1.
CMCNT is initialized to H'0000 by clearing any channels of the counter start bit from 1 to 0 in the
compare match timer start register (CMSTR).
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
13.2.4 Compare Match Constant Register (CMCOR)
CMCOR is a 16-bit register that sets the interval up to a compare match with CMCNT.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 1.00 Mar. 25, 2008 Page 676 of 1868
REJ09B0372-0100