SH7205 Datasheet, PDF (1572/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 29 On-Chip RAM
29.2 Usage Notes
29.2.1 Page Conflict
When the same page of the on-chip high-speed RAM is simultaneously accessed from different
buses, a page conflict occurs. Although each access is completed correctly, such a conflict
degrades the memory access speed. Therefore, it is advisable to provide software measures to
prevent such a conflict. Different pages, instead of the same page, can be simultaneously accessed
from different buses.
29.2.2 RAME Bit and RAMWE Bit
Before clearing the RAME bits of SYSCR1, SYSCR3, SYSCR5, SYSCR7, SYSCR9, and
SYSCR11 to 0 and the RAMWE bits of SYSCR2, SYSCR4, SYSCR6, SYSCR8, SYSCR10, and
SYSCR12 to 0, be sure to read and write the arbitrarily-selected same address in each page.
Otherwise, the data last written to the corresponding page may not beactually written to the RAM.
//For page 0 of on-chip RAM0
MOV.L #H'FFF80000, R0
MOV.L @R0, R1
MOV.L R1, @R0
//For page 1 of on-chip RAM0
MOV.L #H'FFF84000, R0
MOV.L @R0, R1
MOV.L R1, @R0
//For page 2 of on-chip RAM0
MOV.L #H'FFF88000, R0
MOV.L @R0, R1
MOV.L R1, @R0
//For page 3 of on-chip RAM0
MOV.L #H'FFF8C000, R0
MOV.L @R0, R1
MOV.L R1, @R0
//For page 0 of on-chip RAM1
MOV.L #H'FFFA0000, R0
MOV.L @R0, R1
MOV.L R1, @R0
//For page 1 of on-chip RAM1
MOV.L #H'FFFA4000, R0
MOV.L @R0, R1
MOV.L R1, @R0
Figure 29.1 Examples of Read/Write
Rev. 1.00 Mar. 25, 2008 Page 1540 of 1868
REJ09B0372-0100