SH7205 Datasheet, PDF (913/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 18 I²C Bus Interface 3 (IIC3)
Table 18.5 Time for Monitoring SCL
CKS3
CKS2
Time for Monitoring SCL
0
0
9 tpcyc*
1
21 tpcyc*
1
0
33 tpcyc*
1
81 tpcyc*
Note: * tpcyc indicates the frequency of the peripheral clock (Pφ).
18.7 Usage Notes
18.7.1 Note on Setting for Multi-Master Operation
In multi-master operation, when the setting for IIC transfer rate (ICCR1.CKS[3:0]) makes this LSI
slower than the other masters, pulse cycles with an unexpected length will infrequently be output
on SCL.
Be sure to specify a transfer rate that is at least 1/1.8 of the fastest transfer rate among the other
masters.
18.7.2 Note on Master Receive Mode
Reading ICDRR around the falling edge of the 8th clock might fail to fetch the receive data.
In addition, when RCVD is set to 1 around the falling edge of the 8th clock and the receive buffer
full, a stop condition may not be issued.
Use either 1 or 2 below as a measure against the situations above.
1. In master receive mode, read ICDRR before the rising edge of the 8th clock.
2. In master receive mode, set the RCVD bit to 1 so that transfer proceeds in byte units.
18.7.3 Note on Setting ACKBT in Master Receive Mode
In master receive mode operation, set ACKBT before the falling edge of the 8th SCL cycle of the
last data being continuously transferred. Not doing so can lead to an overrun for the slave
transmission device.
Rev. 1.00 Mar. 25, 2008 Page 881 of 1868
REJ09B0372-0100