SH7205 Datasheet, PDF (1585/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 30 Power-Down Modes
Initial
Bit Bit Name Value R/W Description
2
MSTP72 1
R/W Module Stop 72
When set to 1, the clock supply to the SSU1 is halted.
0: SSU1 runs.
1: Clock supply to SSU1 is halted.
1
MSTP71 1
R/W Module Stop 71
When set to 1, the clock supply to the Video IN/2DG/Video
OUT is halted.
0: Video IN/2DG/Video OUT run.
1: Clock supply to Video IN/2DG/Video OUT is halted.
0
MSTP70 1
R/W Module Stop 70
When set to 1, the clock supply to the USB is halted.
0: USB runs.
1: Clock supply to USB is halted.
30.2.8 System Control Register 1 (SYSCR1)
SYSCR1 is an 8-bit readable/writable register that enables or disables access (read/write) from
CPU0 to each page of the high-speed on-chip RAM0.
Setting the RAMEn (n = 0 to 3) bit in SYSCR1 to 1 enables access to page n. Clearing the
RAMEn bit to 0 disables access to page n. In this case, an undefined value is returned when
reading data or fetching an instruction from page n, and writing to page n is ignored. The initial
value of the RAMEn bit is 1.
When clearing the RAMEn bit to 0, be sure to execute instructions to read from and write to the
same arbitrary address in page n before clearing the RAMEn bit. If not executed, the data last
written to page n may not be actually written to the high-speed on-chip RAM.
SYSCR1 should be set by the program that is placed in a space other than the high-speed on-chip
RAM space. Furthermore, an instruction to read SYSCR1 should be located immediately after the
instruction to write to SYSCR1. Otherwise, normal access to the high-speed on-chip RAM is not
guaranteed.
Note: When writing to this register, see section 30.4, Usage Notes.
Rev. 1.00 Mar. 25, 2008 Page 1553 of 1868
REJ09B0372-0100