SH7205 Datasheet, PDF (252/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 7 Interrupt Controller (INTC)
7.11 Data Transfer with Interrupt Request Signals
Interrupt request signals can be used to activate the DMAC and transfer data.
DMA transfer request enable registers 0 to 8 (DREQER0 to DREQER8) are used to specify
whether the interrupt request signals start interrupt exception handling or activate the DMAC.
When the bits corresponding to on-chip peripheral modules are set to 1, DMA transfer requests are
generated; when these bits are set to 0, CPU interrupt requests are generated.
7.12 Usage Note
7.12.1 Timing to Clear an Interrupt Source
The interrupt source flags should be cleared in the interrupt handler. After clearing the interrupt
source flag, "time from occurrence of interrupt request until interrupt controller identifies priority,
compares it with mask bits in the SR, and sends interrupt request signal to CPU" shown in table
7.9 is required before the interrupt source sent to the CPU is actually cancelled. To ensure that an
interrupt request that should have been cleared is not inadvertently accepted again, read the
interrupt source flag after it has been cleared, and then execute an RTE instruction.
Rev. 1.00 Mar. 25, 2008 Page 220 of 1868
REJ09B0372-0100