SH7205 Datasheet, PDF (933/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 19 Serial Sound Interface with FIFO (SSIF)
Initial
Bit
Bit Name Value R/W Description
5, 4
RTRG[1:0] 00
R/W Receive Data Trigger Number
These bits specify the number of received data bytes in
the FIFO (receive trigger number) at which the RDF flag
in the FIFO status register (SSIFSR) is set while the
FIFO is operating for reception.
The RDF flag is set to 1 when the number of received
data bytes in the FIFO data register (SSIFDR) has
become equal to or greater than the set trigger number
shown below.
00: 1
01: 2
10: 4
11: 6
3
—
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2
TIE
0
R/W Transmit Interrupt Enable
Enables or disables generation of transmit data empty
interrupt (TXI) requests in the following situation:
when the FIFO is operating for transmission, the data
for transmission in the FIFO data register (SSIFDR) is
transferred to the transmit data register (SSITDR) and
the number of data bytes in the FIFO data register has
become less than the set transmit trigger number; and
thus the TDE flag in the FIFO status register (SSIFSR)
is set to 1.
0: Transmit data empty interrupt (TXI) request is
disabled
1: Transmit data empty interrupt (TXI) request is
enabled*
Note: * TXI can be cleared by clearing either the TDE
flag (see the description of the TDE bit for
details) or TIE bit.
Rev. 1.00 Mar. 25, 2008 Page 901 of 1868
REJ09B0372-0100