SH7205 Datasheet, PDF (1351/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 25 AT Attachment Packet Interface (ATAPI)
25.4 Operation
The ATAPI interface supports the primary channel as a host. It also supports a master/slave
configuration as stipulated in the ATAPI interface specification. The FIFO read/write buffer of the
ATAPI interface is designed to transfer data at up to 16 Mbytes/s in multiword DMA mode and up
to 33 Mbytes/s in ultra DMA mode. The ATAPI interface supports the 3.3V I/O interface.
The ATA task file register and ATAPI packet command file register are allocated in the on-chip
peripheral module space of this LSI device. Therefore, accessing these registers from the LSI
device can be made by addressing the on-chip register of the DVDROM drive or the like with the
DCS1, DCS0, and DSA2 to DSA0 pins.
25.4.1 Data Transfer Modes
The ATAPI interface control register supports PIO transfer modes, multiword DMA transfer
modes, and ultra DMA transfer modes. The ATAPI interface control register is used to initiate
each transfer mode and set the ATAPI interface timing that varies from one transfer mode to
another.
The transfer modes supported with the ATAPI interface include PIO modes 0 to 4, multiword
DMA modes 0 to 2, and ultra DMA modes 0 to 2.
The enhanced bus is used for multiword and ultra DMA data transfers, and the peripheral bus, for
PIO transfers.
Table 25.5 Data Transfer Modes
Data Transfer Mode
Internal Operation
and Internal Register
PIO Data
Transfer
DMA Data Transfer between ATA Device
and Enhanced Bus
Multiword DMA
Ultra DMA
FIFO operation
Bypass*
Used
Used
UDMAEN bit in control register
Don't Care 0
1
START/STOP bit in control register Not Used
Used
Used
Note: * The CPU accesses the ATA device in PIO mode.
In enhanced bus DMA transfers, data is transferred between the ATAPI device and
memory.
Rev. 1.00 Mar. 25, 2008 Page 1319 of 1868
REJ09B0372-0100