SH7205 Datasheet, PDF (1341/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 25 AT Attachment Packet Interface (ATAPI)
(3) Interrupt enable (ATAPI_INT_ENABLE)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10
-
-
-
-
-
-
Initial value: -
-
-
-
-
-
R/W: R
R
R
R
R
R
9
8
7
6
5
4
3
2
1
0
- iSWERR iIFERR - iDEVTRM iDEVINT iTOUT iERR iNEND iACT
-
0
0
0
0
0
0
0
0
0
R R/W R/W R R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to 9 

R
Reserved
8
iSWERR 0
R/W This bit is an SWERR interrupt enable bit.
7
iIFERR
0
R/W This bit is an IFERR interrupt enable bit.
6


R
Reserved
5
iDEVTRM 0
R/W This bit is a DEVTRM interrupt enable bit.
4
iDEVINT 0
R/W This bit is a DEVINT interrupt enable bit.
3
iTOUT
0
R/W This bit is a TOUT interrupt enable bit.
2
iERR
0
R/W This bit is an ERR interrupt enable bit.
1
iNEND
0
R/W This bit is an NEND interrupt enable bit.
0
iACT
0
R/W This bit is an ACT interrupt enable bit. It is not
recommended to set the bit to 1, because ACT is
cleared automatically when a DMA transfer is
completed.
Note: Writing 1 to each bit enables the interrupt signal corresponding to each bit in the ATAPI
status register.
Rev. 1.00 Mar. 25, 2008 Page 1309 of 1868
REJ09B0372-0100