SH7205 Datasheet, PDF (926/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 19 Serial Sound Interface with FIFO (SSIF)
Initial
Bit
Bit Name Value R/W Description
7 to 4 CKDV[3:0] 0000 R/W Serial Oversampling Clock Division Ratio
Sets the ratio between the oversampling clock (AUDIOφ)
and the serial bit clock. When the SCKD bit is 0, the
setting of these bits is ignored. The serial bit clock is
used in the shift register and is supplied from the
SSISCK pin.
0000: AUDIOφ
0001: AUDIOφ/2
0010: AUDIOφ/4
0011: AUDIOφ/8
0100: AUDIOφ/16
0101: AUDIOφ/32
0110: AUDIOφ/64
0111: AUDIOφ/128
1000: AUDIOφ/6
1001: AUDIOφ/12
1010: AUDIOφ/24
1011: AUDIOφ/48
1100: AUDIOφ/96
1101: Setting prohibited
1110: Setting prohibited
1111: Setting prohibited
3
MUEN
0
R/W Mute Enable
0: Module is not muted.
1: Module is muted.
2

0
R
Reserved
The read value is undefined. The write value should
always be 0.
1
TRMD
0
R/W Transmit/Receive Mode Select
0: Module is in receive mode.
1: Module is in transmit mode.
0
EN
0
R/W SSIF Module Enable
0: Module is disabled.
1: Module is enabled.
Rev. 1.00 Mar. 25, 2008 Page 894 of 1868
REJ09B0372-0100