SH7205 Datasheet, PDF (1410/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 2D Graphics Engine (2DG)
26.3.24 Mixing Mode Setting Register for Output Block (MGR_MIXMODE)
The register MGR_MIXMODE sets mixing mode for the output block. The register value is
applied to the output block in synchronization with the VSYNC signal. For details, see section
26.4.4 (5), Blending in Output Block.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
- NTSC -
-
-
-
CHG_A
-
FCFD
Initial value: -
-
-
0
-
-
-
-
0
0
0
0
-
0
0
0
R/W: R
R
R R/W R
R
R
R R/W R/W R/W R/W R R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
- MVON -
-
- CBCR -
-
-
-
-
-
- VLD_N
Initial value: -
-
-
0
-
-
-
0
-
-
-
-
-
-
-
0
R/W: R
R
R R/W R
R
R R/W R
R
R
R
R
R
R R/W
Bit
Bit name
31 to 29 
28
NTSC
27 to 24 
23 to 20 CHG_A
19

18 to 16 FCFD
Initial
Value
R/W
Undefined R
0
R/W
Undefined R
0000
R/W
Undefined R
000
R/W
Description
Reserved
The read value is undefined. The write value should
always be 0.
Output Block NTSC/PAL
This bit sets NTSC/PAL for the output block.
0: NTSC
1: PAL
Reserved
The read value is undefined. The write value should
always be 0.
Output Block α Value Replacement Data
These bits set data to be replaced with α value in the
αRGB555 format for the output block.
Reserved
The read value is undefined. The write value should
always be 0.
Output Block α Blending Value
These bits set an α-blending value for output block.
Cp = (Fc × Cdc) + (Fd × Cv) is output from the
blending section on the output block.
For the combination, see the following table.
Rev. 1.00 Mar. 25, 2008 Page 1378 of 1868
REJ09B0372-0100