SH7205 Datasheet, PDF (911/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 18 I²C Bus Interface 3 (IIC3)
18.6 Bit Synchronous Circuit
In master mode, this module has a possibility that high level period may be short in the two states
described below.
• When SCL is driven to low by the slave device
• When the rising speed of SCL is lowered by the load of the SCL line (load capacitance or pull-
up resistance)
Therefore, it monitors SCL and communicates by bit with synchronization.
Figure 18.22 shows the timing of the bit synchronous circuit and table 18.5 shows the time when
the SCL output changes from low to Hi-Z then SCL is monitored.
Rev. 1.00 Mar. 25, 2008 Page 879 of 1868
REJ09B0372-0100