SH7205 Datasheet, PDF (38/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 1 Overview
Items
Specification
Direct memory access • 14 channels:
controller (DMAC)
Two-dimensional addressing supported on eight channels
• Transfer requests
Software trigger, on-chip peripheral I/O request, and requests from
external pins
• Number of bytes for transfer: 64 Mbytes at maximum
• Transfer data size
Single-data transfer: 8 bits, 16 bits, or 32 bits
Single-operand transfer: 1,2, 4, 8, 16, 32, 64, 128 units of data
Non-stop transfer: Until the byte counter reaches 0
• Transfer mode
 Cycle stealing mode (dual-address transfer): 3 clock cycles at
minimum per data transfer
 Pipelined transfer (dual-address transfer): 1 clock cycle at
minimum per data transfer
• Address direction control
Fixed, incremental, decremental, rotate, and two-dimensional
addressing
• Selectable DMA transfer condition
Single-operand transfer, consecutive operand transfer, and non-stop
transfer
• Reloading: source address, destination address, byte counter
Rev. 1.00 Mar. 25, 2008 Page 6 of 1868
REJ09B0372-0100