SH7205 Datasheet, PDF (1269/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Bit
Bit Name
15
BSTS
14
INBUFM
Section 24 USB 2.0 Host/Function Module (USB)
Initial
Value R/W
0
R
0
R
Description
Buffer Status
Indicates whether the FIFO buffer assigned to the
corresponding pipe is accessible from the CPU.
The meaning of this bit depends on the settings of
the DIR, BFRE, and DCLRM bits as shown in table
24.13.
0: Buffer not accessible
1: Buffer accessible
IN Buffer Monitor
When the pertinent pipe is in the transmitting
direction (DIR = 1), this bit indicates 1 when writing
of data to at least one FIFO buffer plane is
completed.
This bit indicates 0 when this module completes
transmitting the data in the FIFO buffer plane to
which all the data has been written. In double buffer
mode (DBLB = 1), this bit indicates 0 when this
module completes transmitting the data in the two
FIFO buffer planes before writing of data to one FIFO
buffer plane is completed.
This bit indicates the same value as the BSTS bit
when the pertinent pipe is in the receiving direction
(DIR = 0).
0: There is no data to be transmitted in the buffer
memory.
1: There is data to be transmitted in the buffer
memory.
Rev. 1.00 Mar. 25, 2008 Page 1237 of 1868
REJ09B0372-0100