SH7205 Datasheet, PDF (1270/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name Value
R/W Description
13
CSCLR
0
R/W*² C-Split Status Clear Bit
Set this bit to 1 to clear the CSSTS bit of the
pertinent pipe.
When the host controller function is selected, setting
this bit to 1 allows this module to clear the CSSTS bit
to 0.
For the transfer using the split transaction, to restart
the next transfer with the S-Split forcibly, set this bit
to 1. However, for the normal split transaction, this
module automatically clears the CSSTS bit to 0 upon
completion of the C-Split; therefore, processing for
clearing the CSSTS bit is not necessary.
Controlling the CSSTS bit through this bit must be
done while UACT is 0 and thus communication is
halted or while no transfer is being performed with
bus disconnection detected.
0: Writing invalid
1: Clears the CSSTS bit to 0.
Note: Setting this bit to 1 while CSSTS is 0 has no
effect.
12
CSSTS
0
R
CSSTS Status Bit
Indicates the C-Split status of the split transaction of
the pertinent pipe when the host controller function is
selected.
This bit indicates 1 upon start of the C-Split and
indicates 0 upon detection of C-Split completion.
0: S-Split transaction being processed or the transfer
not using the split transaction in progress
1: C-Split transaction being processed
11

Undefined R
Reserved
Undefined value is read from this bit. The write value
should always be 0.
Rev. 1.00 Mar. 25, 2008 Page 1238 of 1868
REJ09B0372-0100