SH7205 Datasheet, PDF (1435/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 2D Graphics Engine (2DG)
• The following are examples of CPU-side settings for using a DMA transfer:
The number of pixels transferred to the 2DG is 52 pixels (horizontal width) × 20 vertical lines,
and the size to be transferred is 32 bits.
During normal DMA use: The amount of DMA transfer per operation is 52 pixels; if transfers
are made by reloading 20 times, the OPSEL bits of the DMA mode
register must be set to an integer multiple of 52 pixels. For this
purpose, a transfer of two data items/operand must be set.
During use of a two-dimensional DMAC: The following settings must be specified: number of
blocks per line DBN = 1; number of lines per block,
DRN = 20; number of column data items per block,
DCDN = 26 data items; OPSEL = 2 data
items/operand.
• The number of data items transferred per operand, which is a transfer parameter on the DMA
side, can be any value; however, on some transfer areas the situation can arise where one line
of data transfer cannot be finished within an HSYNC period (causing an underflow). If this
problem occurs, it can be verified by checking the INT_UDRFL bit of the GR_IRSTAT
register. If an underflow occurs, increase the number of data items transferred per operand on
the DMA side.
• During a data write transfer to the SE, SB, or SA buffer or during a data read transfer from the
DC buffer, in either case, DMA transfer or CPU transfer, internally the 2DG processes data by
re-assigning internally-generated address. For this reason, even when the CPU side performs a
data transfer from any address in the applicable memory space, the 2DG side performs access
beginning with the first address in the memory space.
• The direction control bit of the DMAC during a destination transfer from the DMAC to the SE,
SB, or SA buffer of the 2DG or during a source transfer from the DC buffer, targets on
increment (memory-to-memory image) (memory-to-I/O transfers are prohibited).
• Operation during a CPU transfer
If data access to the 2DG is to be made using the CPU transfer instead of a DMA transfer, the
transfer must be performed by taking the maximum capacity of the applicable buffer into
consideration (during a DMA transfer, the buffer size is controlled by internal hardware and,
therefore, it need not be considered).
For example, if an image consisting of 60 pixels × 4 lines (for a total of 240 pixels) is to be
transferred to the SB buffer by means of CPU transfer,
Rev. 1.00 Mar. 25, 2008 Page 1403 of 1868
REJ09B0372-0100