SH7205 Datasheet, PDF (476/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
(2) Edge Sense
If an edge sense (STRG = 00 or 10) is selected, transition to a rising or falling edge of a DMA
request signal is recognized as a DMA request.
When a valid edge is detected, the DMA request bit (DREQ) of DMA control register B
(DMCNTBn) is set to 1. The value of this bit is retained even if the input level of the DMA
request signal changes later. When a DMA request is accepted and the DMA acknowledge signal
is effectively output, the DMA request bit (DREQ) bit is automatically cleared to 0.
In this way, retention of DMA requests in edge sense mode is determined from the value of the
DMA request bit (DREQ). For this reason, if the DMA request bit (DREQ) is set to 1, the edges
selected according to new DMA request signals are ignored. Figure 11.10 shows an example of
DMA acceptance processing when an edge sense is selected.
CKIO
Start of single operand transfer
DMAC state
(internal state)
DREQ0 to DREQ3
(falling edge sense)
Read
Write
Read
DMA acknowledge output
DMA request bit
The DMA request bit is set
when a valid edge is detected.
The value of the DMA request bit
is retained even if the input level
of the DMA request changes.
If the valid bit of a DMA request is detected
when the DMA request bit is cleared,
the DMA request bit is set again.
(A single DMA request is retained.)
[Legend]
When a DMA request is accepted, the DMA acknowledge signal
is effectively output and the DMA request bit is cleared.
: Sampling point for DMA request signal
Figure 11.10 Example of DMA Request Acceptance Processing When an Edge Sense Is
Selected
Rev. 1.00 Mar. 25, 2008 Page 444 of 1868
REJ09B0372-0100