SH7205 Datasheet, PDF (1825/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 33 Electrical Characteristics
33.4.10 IIC3 Timing
Table 33.15 IIC3 Timing
Conditions: VCC = PLLVCC = 1.1 to 1.3 V, USBDVCC = 1.1 to 1.3 V, USBAVCC = 1.1 to 1.3 V,
PVCC = 3.0 to 3.6 V, AVCC = 3.0 to 3.6 V, USBAPVCC = 3.0 to 3.6 V,
2DGAPVCC0 = 3.0 to 3.6 V, 2DGAPVCC1 = 3.0 to 3.6 V,
VSS = PLLVSS = USBAVSS = AVSS = USBAPVSS = 2DGAPVSS0 = 2DGAPVSS1 = 0 V,
Ta = −20 to 85 °C
Item
Symbol
Min.
SCL input cycle time
t_SCL
SCL input high pulse width
t_SCLH
SCL input low pulse width
t_SCLL
SCL, SDA input rise time
t_Sr
SCL, SDA input fall time
t_Sf
SCL, SDA input spike pulse
t_SP
removal time*²
12
t *1
pcyc
+
600
3
t *1
pcyc
+
300
5
t *1
pcyc
+
300



SDA input bus free time
t_BUF
5
Start condition input hold time t_STAH
3
Retransmit start condition input t_STAS
3
setup time
Stop condition input setup time t_STOS
Data input setup time
t_SDAS
3
1
t *1
pcyc
+
20
Data input hold time
t_SDAH
0
SCL, SDA capacitive load
Cb
0
SCL, SDA output fall time*³
t_Sf

Notes:
1.
t
pcyc
indicates
the
peripheral
clock
(Pφ)
cycle.
2. Depends on the value of NF2CYC.
3. Indicates the I/O buffer characteristic.
Max.



300
300
1, 2






400
250
Unit
ns
ns
ns
ns
ns
t *¹
pcyc
t *1
pcyc
t *1
pcyc
t *1
pcyc
t *1
pcyc
ns
ns
pF
ns
Figure
Figure 33.35
Rev. 1.00 Mar. 25, 2008 Page 1793 of 1868
REJ09B0372-0100