SH7205 Datasheet, PDF (1107/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 AND/NAND Flash Memory Controller (FLCTL)
Bit
15
14
13, 12
11, 10
Initial
Bit Name Value R/W
FCKSEL 0
R/W
—
0
R
ECCPOS 00
R/W
[1:0]
ACM[1:0] 00
R/W
Description
Flash Clock Select
Selects the dividing rate of clock FCLK in the flash
memory. This bit is used together with QTSEL. Refer to
the description of QTSEL.
Reserved
This bit is always read as 0. The write value should
always be 0.
ECC Embedding Position Specification
ECCPOS[2:0] (bits 25, 13, and 12 of this register)
specifies the position to place ECC in the control code
field when 3- or 4-symbol ECC circuit is used
• When 4ECCEN = 0 (ECC is eight bytes)
000: Places ECC with offset of 512 bytes in a sector
001: Places ECC with offset of 516 bytes in a sector
010: Places ECC with offset of 520 bytes in a sector
Other than above: Setting prohibited
• When 4ECCEN = 1 (ECC is ten bytes)
000: Places ECC with offset of 518 bytes in a sector
001: Places ECC with offset of 517 bytes in a sector
010: Places ECC with offset of 516 bytes in a sector
011: Places ECC with offset of 515 bytes in a sector
100: Places ECC with offset of 514 bytes in a sector
101: Places ECC with offset of 513 bytes in a sector
110: Places ECC with offset of 512 bytes in a sector
111: Setting prohibited
Access Mode Specification 1 and 0
Specify access mode.
00: Command access mode
01: Sector access mode
10: Setting prohibited
11: Setting prohibited
Rev. 1.00 Mar. 25, 2008 Page 1075 of 1868
REJ09B0372-0100