SH7205 Datasheet, PDF (1125/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 AND/NAND Flash Memory Controller (FLCTL)
23.3.10 Ready Busy Timeout Counter (FLBSYCNT)
FLBSYCNT is a 32-bit read-only register.
The status of flash memory obtained by the status read is stored in the bits STAT[7:0].
The timeout time set in the bits RBTMOUT[19:0] in FLBSYTMR is copied to the bits
RBTIMCNT[19:0] and counting down is started when the FRB pin is placed in a busy state. When
values in the RBTIMCNT[19:0] become 0, 1 is set to the BTOERB bit in FLINTDMACR, thus
notifying that a timeout error has occurred. In this case, an FLSTE interrupt request can be issued
if an interrupt is enabled by the RBERINTE bit in FLINTDMACR.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STAT[7:0]
-
-
-
-
RBTIMCNT[19:16]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RBTIMCNT[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit
Bit Name
31 to 24 STAT[7:0]
23 to 20 —
Initial
Value R/W
All 0 R
All 0 R
19 to 0 RBTIMCNT[19:0] H'00000 R
Description
Indicate the flash memory status obtained by the
status read.
Reserved
These bits are always read as 0.
Ready Busy Timeout Counter
When the FRB pin is placed in a busy state, the
values of the bits RBTMOUT[19:0] in FLBSYTMR
are copied to these bits. These bits are counted
down while the FRB pin is busy. A timeout error
occurs when these bits are decremented to 0.
Rev. 1.00 Mar. 25, 2008 Page 1093 of 1868
REJ09B0372-0100