SH7205 Datasheet, PDF (322/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
10.4.10 SDRAM Initialization Register 1 (SDIR1)
SDIR1 controls activation of the SDRAM initialization sequence.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- DINIST
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- DINIRQ
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R R/W
Initial
Bit
Bit Name Value
31 to 17 
All 0
16
DINIST 0
15 to 1 
All 0
0
DINIRQ 0
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Initialization Status
When set to 1, this bit indicates that an SDRAM
initialization sequence is in progress for the channel for
SDRAM0 or SDRAM1.
0: Initialization sequence not in progress
1: Initialization sequence in progress
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Common Initialization Sequence Start
Setting this bit to 1 causes the SDRAM initialization
sequence to start and automatically sets the initialization
status bit (DINIST) to 1. The initialization status bit
(DINIST) is cleared automatically after the initialization
sequence ends. The value written to the DINIRQ bit is not
retained.
0: Invalid
1: Initialization sequence start
Rev. 1.00 Mar. 25, 2008 Page 290 of 1868
REJ09B0372-0100