SH7205 Datasheet, PDF (1182/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
24.3.7 Test Mode Register (TESTMODE)
TESTMODE is a register that controls the USB test signal output during high-speed operation.
This register is initialized by a power-on reset.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
—
—
—
—
UTST[3:0]
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R R/W R/W R/W R/W
Bit
Bit Name
15 to 4 
3 to 0 UTST[3:0]
Initial
Value
R/W
Undefined R
0000
R/W
Description
Reserved
Undefined values are read from these bits. The write
value should always be 0.
Test Mode
Controls the output of USB test signals in high-speed
operation. Table 24.8 shows the test mode operation
of this module.
These bits are valid only during high-speed
operation. RHST = 11 in DVSTCTR should be
confirmed before use.
UTST3 differs depending on the controller function
select bit (DCFM) setting. UTST3 should be set
based on the DCFM bit.
After a test has been executed with these bit
settings, this module should be returned from test
mode by a system reset.
Rev. 1.00 Mar. 25, 2008 Page 1150 of 1868
REJ09B0372-0100