SH7205 Datasheet, PDF (1604/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 30 Power-Down Modes
(b) Canceling by a reset
Single-processor mode is canceled and the reset exception handling is executed by a power-on
reset or manual reset, and then the LSI enters dual-processor mode.
30.3.4 Dual-Sleep Mode
(1) Transition to Dual-Sleep Mode
In single-processor mode where CPU0 or CPU1 is running, the LSI can enter dual-sleep mode.
Executing the SLEEP instruction by CPU0 when the STBY bit in STBCR1 is 0 in single-
processor 0 mode causes a transition from the program execution state to dual-sleep mode.
However, if CPU0 executes the SLEEP instruction when the SLPERE bit in STBCR1 is 1, the LSI
does not enter dual-sleep mode and a sleep error exception occurs.
On the other hand, when CPU1 executes the SLEEP instruction in single-processor 1 mode, CPU1
switches from the program execution state to dual-sleep mode. The LSI enters dual-sleep mode
irrespective of the value of the STBY bit in STBCR1.
The running CPU halts after executing the SLEEP instruction, but the contents of its registers
remain unchanged. The on-chip peripheral modules continue to operate. The CKIO pin continues
to output the clock.
(2) Canceling Dual-Sleep Mode
Dual-sleep mode is canceled by an interrupt (NMI, IRQ, PINT, on-chip peripheral module
interrupt, and inter-processor interrupt) or a reset (manual reset or power-on reset).
(a) Canceling by an interrupt
When an NMI, IRQ, on-chip peripheral module interrupt, or inter-processor interrupt occurs,
single-processor mode is canceled and interrupt exception handling is executed. The following
transition depends on the setting of the interrupt enable bit that controls enabling/disabling of
acceptance of interrupts by each CPU. When both CPUs are enabled to accept interrupts, the LSI
enters dual-processor mode. When only CPU0 (CPU1) is enabled to accept interrupts, the LSI
enters single-processor 0 (single-processor 1) mode. For details of the interrupt enable bit, see
section 7, Interrupt Controller (INTC). If the priority level of the interrupt occurred is not higher
than the interrupt mask level that is set in SR of the CPU, the interrupt request is not accepted and
single-processor mode is not canceled.
Rev. 1.00 Mar. 25, 2008 Page 1572 of 1868
REJ09B0372-0100